| PART |
Description |
Maker |
| PLL103-03 PLL103-03XC PLL103-03XI PLL103-03XM |
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS
|
PhaseLink Corporation
|
| ICS93735 ICS93735F-T |
DDR Phase Lock Loop Zero Delay Clock Buffer
|
ICS
Integrated Circuit Systems
|
| 1514 1514-22.5Y 1514-135Y 1514-2.5A 1514-130D 1514 |
Delay 50 /-2.5 ns, fixed SIP delay line Td/Tr=5
Delay 60 /-3 ns, fixed SIP delay line Td/Tr=5
Delay 45 /-2.3 ns, fixed SIP delay line Td/Tr=5
Delay 40 /-2 ns, fixed SIP delay line Td/Tr=5
Delay 270 /-13.5 ns, fixed SIP delay line Td/Tr=5
Delay 25 /-1.3 ns, fixed SIP delay line Td/Tr=5
Delay 170 /-8.5 ns, fixed SIP delay line Td/Tr=5
Delay 120 /-6 ns, fixed SIP delay line Td/Tr=5
Delay 10 /-1 ns, fixed SIP delay line Td/Tr=5
Delay 90 /-4.5 ns, fixed SIP delay line Td/Tr=5
Delay 70 /-3.5 ns, fixed SIP delay line Td/Tr=5
Delay 130 /-6.5 ns, fixed SIP delay line Td/Tr=5
Delay 135 /-6.8 ns, fixed SIP delay line Td/Tr=5
PASSIVE DELAY LINE, TRUE OUTPUT, PSIP4
Fixed passive SIP delay line
Delay 2.5 /-1 ns, fixed SIP delay line Td/Tr=5
Delay 3.5 /-1 ns, fixed SIP delay line Td/Tr=5
Delay 100 /-5 ns, fixed SIP delay line Td/Tr=5
Delay 105 /-5.3 ns, fixed SIP delay line Td/Tr=5
Delay 140 /-7 ns, fixed SIP delay line Td/Tr=5
Delay 150 /-7.5 ns, fixed SIP delay line Td/Tr=5
Delay 15 /-1 ns, fixed SIP delay line Td/Tr=5
Delay 20 /-1 ns, fixed SIP delay line Td/Tr=5
Delay 22.5 /-1.2 ns, fixed SIP delay line Td/Tr=5
Delay 30 /-1.5 ns, fixed SIP delay line Td/Tr=5
Delay 37.5 /-1.9 ns, fixed SIP delay line Td/Tr=5
Delay 80 /-4 ns, fixed SIP delay line Td/Tr=5
Delay 7.5 /-1 ns, fixed SIP delay line Td/Tr=5
|
DATA DELAY DEVICES INC
|
| IDT72T4088 IDT72T4088L10BB IDT72T4088L10BBI IDT72T |
2.5 VOLT HIGH-SPEED TeraSync DDR/SDR FIFO 40-BIT CONFIGURATION
2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
|
IDT[Integrated Device Technology]
|
| CY2309CZXI-1 CY2309CZXI-1H CY2309CZXI-1HT CY2309CZ |
3.3 V Zero Delay Clock Buffer
3.3V Zero Delay Clock Buffer 2309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
|
Cypress Semiconductor, Corp.
|
| PLL102-108XC PLL102-108XI PLL102-108XM PLL102-108 |
Programmable DDR Zero Delay Clock Driver
|
PLL[PhaseLink Corporation]
|
| PLL102-109XI PLL102-109XC PLL102-109XM PLL102-109 |
Programmable DDR Zero Delay Clock Driver
|
PLL[PhaseLink Corporation]
|
| UPD424263LLE-A80 UPD424263LLE-A70 UPD424263LG5M-A6 |
20-output, 200-MHz Zero Delay Buffer
16 Kbit (2K x 8) nvSRAM
3.3V Zero Delay Buffer
x16 Fast Page Mode DRAM
Three-PLL General-Purpose EPROM Programmable Clock Generator
Phase-Aligned Clock Multiplier x16快速页面模式的DRAM
|
Cooper Hand Tools
|
| MC74LVX126 MC74LVX126D MC74LVX126M MC74LVX126MEL L |
Quad Bus Buffe With 5V−Tolerant Inputs
|
ONSEMI[ON Semiconductor]
|
| ASM5I23S08AG-4-16-SR ASM5P23S08AG-4-16-SR ASM5I23S |
23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
3.3V ‘SpreadTrak?/a> Zero Delay Buffer
3.3V ‘SpreadTrak Zero Delay Buffer
3.3V 隆庐SpreadTrak隆炉 Zero Delay Buffer
|
PulseCore Semiconductor
|
| ICS93725 ICS93725YFT |
DDR and SDRAM Zero Delay Buffer
|
ICST[Integrated Circuit Systems]
|
| CY28341-3 CY28341OC-3 CY28341OC-3T CY28341ZC-3 CY2 |
Universal Clock Chip for VIA?P4M/KT/KM400A DDR Systems
Universal Clock Chip for VIA?⑿4M/KT/KM400A DDR Systems
Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems
|
SpectraLinear Inc
|
